Network echo canceler chips are designed to handle several channels simultaneously. With the processing speeds now available, a single chip might handle several hundred channels. In current implementations, however, the adaptation algorithm is designed for a single channel, and the computations are replicated N c times, where N c is the number of channels. With such an implementation, the computational requirement is N c times the peak load for a single channel. The number of computations required in each channel, however, varies widely over time. Therefore, a considerable reduction in computational load can be achieved by designing the system for the average load plus a margin to account for load variations. The reduction in complexity is achieved by exploiting three features: (a) the inherent pauses in conversations; (b) the sparseness of network echo paths; and (c) the fact that an adaptive filter does not need to be updated when the error signal is small. It is shown that, in principle, such a design can reduce the computational load by a very large factor - perhaps as large as thirty. It remains to be seen whether a customized hardware architecture can be implemented to take advantage fully of the proposed algorithm

Meeting Name

2001 IEEE International Conference on Acoustics, Speech, and Signal Processing, 2001. ICASSP '01


Electrical and Computer Engineering

Keywords and Phrases

Adaptation Algorithm; Adaptive Filters; Adaptive Signal Processing; Average Load; Channel; Computational Load Reduction; Conversation Pauses; Digital Signal Processing Chips; Dynamic Resource Allocation; Echo Suppression; Load Variation Margin; Network Echo Canceler Chips; Network Echo Cancellation; Network Echo Path Sparseness; Speech Processing; Telephony

Document Type

Article - Conference proceedings

Document Version

Final Version

File Type





© 2001 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Publication Date

01 Jan 2001