Abstract
An approach is presented for power integrity analysis on multi-layer printed circuit boards in this paper. Two critical current paths are analyzed. Inductance decomposition is applied to identify the critical parameters that can influence the PDN input impedance. Two types of stack-ups are used to perform sensitivity analysis to illustrate the effectiveness of PDN design guidelines. Based on the analysis of the inductance contribution from different blocks in the PCB PDN, a systematic approach to obtain a complete understanding of PDN behavior is proposed. The approach can be used to provide design guidance in PDN design practice.
Recommended Citation
B. Zhao and S. Bai and S. Connor and S. Scearce and M. Cocchini and B. Achkir and A. E. Ruehli and B. Archambeault and J. Fan and J. L. Drewniak, "Systematic Power Integrity Analysis based on Inductance Decomposition in a Multi-Layered PCB PDN," IEEE Electromagnetic Compatibility Magazine, vol. 9, no. 4, pp. 80 - 90, article no. 9327998, Institute of Electrical and Electronics Engineers, Oct 2020.
The definitive version is available at https://doi.org/10.1109/MEMC.2020.9327998
Department(s)
Electrical and Computer Engineering
Publication Status
Open Access
Keywords and Phrases
current path; PDN impedance; Power distribution network
International Standard Serial Number (ISSN)
2162-2272; 2162-2264
Document Type
Article - Journal
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2024 Institute of Electrical and Electronics Engineers, All rights reserved.
Publication Date
01 Oct 2020
Comments
National Science Foundation, Grant IIP-1916535