Implementation issues represent an unfamiliar challenge to most control engineers, and many techniques for controller design ignore these issues outright. Consequently, the design of controlled for smart structural systems usually proceeds without regard for their eventual implementation, thus resulting either in serious performance degradation or in hardware requirements that squander power, complicate integration, and drive up cost the level of integration assumed by the smart patch further exacerbates these difficulties, and any design inefficiency may render the realization of a single-package sensor-controller-actuator system infeasible. The goal of this research is to automate the controller implementation process and to relieve the design engineer of implementation concerns like quantization, computational efficiency, and device selection. Field programmable gate arrays (FPGA) are specifically targeted as a hardware platform because these devices are highly flexible, power efficient, and reprogrammable. The current study develops an automated implementation sequence that minimizes hardware requirements while maintaining controller performance. Beginning with a state space representation of the controller, the sequence automatically generates a configuration bitstream for suitable FPGA implementation MATLAB functions optimize and simulate the control algorithm before translating it into the VHSIC hardware description language (VHDL). These functions improve power efficiency and simplify integration in the final implementationally by performing a linear transformation that renders the controller computationally friendly. The transformation favors sparse matrices in order to reduce multiply operations and the hardware necessary to support them; simultaneously, the remaining matrix elements take on values that minimize limit cycles and parameter sensitivity. The proposed controller design methodology is implemented on simple cantilever beam test structure using FPGA hardware. The experimental closed loop response is gathered for an automated FPGA controller implementation. Finally, the integration of FPGA based controllers into a multi-chip module (MCM) is explored, which represents the next step towards the realization of the smart patch.


Electrical and Computer Engineering

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Article - Journal

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Publication Date

01 Oct 1997