Scalability of Globally Asynchronous QCA (Quantum-Dot Cellular Automata) Adder Design


The concept of clocking for QCA, referred to as the four-phase clocking, is widely used. However, inherited characteristics of QCA, such as the way to hold state, the way to synchronize data flows, and the way to power QCA cells, make the design of QCA circuits quite different from VLSI and introduce a variety of new design challenges. The most severe challenges are due to the fact that the overall timing of a QCA circuit is mainly dependent upon its layout. This issue is commonly referred to as the "layout = timing" problem. To circumvent the problem, a novel self-timed circuit design technique referred to as the Locally Synchronous, globally asynchronous design for QCA has been recently proposed. The proposed technique can significantly reduce the layout-timing dependency from the global network of QCA devices in a circuit; therefore, considerably flexible QCA circuit design is be possible. Also, the proposed technique is more scalable in designing large-scale systems. Since a less number of cells is used, the overall area is smaller and the manufacturability is better. In this paper, numerous multi-bit adder designs are considered to demonstrate the layout efficiency and robustness of the proposed globally asynchronous QCA design technique.


Electrical and Computer Engineering

Keywords and Phrases

Asynchronous Architecture; GCA (Quantum-Dot Cellular Automata); Layout Timing Problem; Robustness (Control Systems); Scalability; Asynchronous Sequential Logic; Quantum Electronics; Cellular Automata

International Standard Serial Number (ISSN)

0923-8174; 1573-0727

Document Type

Article - Journal

Document Version


File Type





© 2008 Springer Verlag, All rights reserved.

Publication Date

01 Jun 2008