With the Trend of Higher Integration, 3D/2.5D IC Solutions Such as CoWoS (Chip-On-Wafer-On-Substrate) Have Become More Popular in Recent Years. Power Integrity (PI) is Always a Critical Part of the Design Especially When the Power Consumption Requirements Are Important Specs for High-Performance Computing. DC-IR Drop is One of the Criteria within Power Integrity Considerations. However, Ordinary Electrical-Only Simulation for DC-IR Drop Will Be an Underestimation Because It Neglects the Copper Conductivity Dropping Due to the Temperature Rising. Thus, an Engineering Solution for Electrical-Thermal Co-Simulation is Important to Help to Provide Both an Accurate PI Analysis and the Proper Mitigations of the IR Drop Along the Power Rails. This Paper Uses a 2. 5D IC Chiplet as an Example to Conduct the Thermal-Aware DC-IR Simulation Workflow. by Iterating and Exchanging the Power Map and Temperature Map Files between an Electrical Simulator and a Thermal Simulator, Detailed Layer-By-Layer IR Drops and the Temperature Map Results Can Provide Good Insights for Efficiently Mitigating the IR Drop for PI by Establishing a Better Cooling Condition in Thermal Solution.


Electrical and Computer Engineering

Keywords and Phrases

2.5D IC; chiplet; co-simulation; DC-IR; interposer; package; thermal

Document Type

Article - Conference proceedings

Document Version


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Publication Date

01 Jan 2023