Conductor Loss Caused by Conductor Surface Roughness is a Critical Aspect in the Design of High-Speed Electronic Systems Since It Significantly Affects their Performances. Well-Established Roughness Models Have Been Proposed over the Years but They Have Been Applied Only to the Transmission Line Models of Interconnects. Typically, the Roughness Models Are Used to Modify the Per-Unit-Length Impedance of the Transmission Line Which is Extracted by 2D Model Methods. The Aim of This Work is to overcome This Limitation Thus Making It Possible to Model Roughness Conductors in the Framework of 3D Full-Wave Methods. More Precisely, it is Presented How to Incorporate Roughness Models in Partial Element Equivalent Circuits (PEEC) Models. the Concept of Surface Impedance Allows a Straightforward Inclusion of Roughness Models in 3D Full-Wave PEEC Models. Numerical Results Are Presented for a Microstrip Line Confirming the Accuracy of the Proposed Approach Compared to Those Obtained using Standard TL Models and a Commercial Tool.


Electrical and Computer Engineering

Keywords and Phrases

insertion loss; Partial Element Equivalent Circuit method; roughness; signal integrity

Document Type

Article - Conference proceedings

Document Version


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Publication Date

01 Jan 2023