Nanowire Crossbar PLA with Adaptive Variable Redundancy


Fundamental electronic structures such as Diodes and FETs have been shown to be constructed using selectively doped semiconducting Carbon Nanotubes or Silicon Nanowires (CNTs, SiNWs) at nanometer scale. Memory and Logic cores s have been proposed, that use the configurable junctions in 2-D crossbars of CNTs. These Memory and Logic arrays at this scale exhibit a significant amount of defects that account for poor a yield. Configuration of these devices in the presence of defects demands an overhead in terms of area and programming time. This work introduces a PLA configuration that makes use of design-specific redundancy in terms of the number of nanowires. This is done in order to simplify the process of programming the PLA, increase the yield, reduce the time complexity, and in turn, reduce the cost of the system.

Meeting Name

2008 International Conference on Computer Design, CDES 2008 (2008: Jul. 14-17, Las Vegas, NV)


Electrical and Computer Engineering

Keywords and Phrases

PLA; VLSI; Architecture; Arrays; Fault-Tolerant; Nanofabric; Nanotechnology

Document Type

Article - Conference proceedings

Document Version


File Type




Publication Date

17 Jul 2008

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