Design for Test Methodology for the IBM PowerPC™ 440 Embedded Core
This paper presents a Design-for-Test (DFT) methodology for the IBM PowerPC™ 440 embedded processors implemented in 130 nm technology. The paper discusses highlights of the DFT techniques that address challenges of achieving highly testable and debuggable product. The paper addresses enhancements of debugging by providing better tracking of initial silicon capabilities for improved yield and time-to-market.
W. K. Al-Assadi and T. A. Dick, "Design for Test Methodology for the IBM PowerPC™ 440 Embedded Core," Proceedings of the International Conference on Computer Design, CSREA Press, Jun 2005.
Electrical and Computer Engineering
Keywords and Phrases
BIST; Design for Test (DFT); IBM; PowerPC; Microprocessors; Scan
Article - Conference proceedings
© 2005 CSREA Press, All rights reserved.
01 Jun 2005