The front surface of a p-n junction solar cell has resistive losses associated with the diffused layer, the metal-semiconductor contact, and the grid structure. These losses are analyzed by considering the spatially distributed nature of the p-n junction and the grid conductors. This distributed diode analysis is especially useful for solar cells operated under concentrated sunlight conditions. The results show the dependence of the V-I characteristics and the maximum power output per unit cell on the ratio of the diffused layer resistance to the junction dynamic resistance. This ratio can assist the designer in establishing proper grid structure geometries and should typically be less than 0.1 if the power output per unit cell is to be within 3 percent of that for the lossless case. Experimental measurements are reported which confirm the theoretical calculations. An analysis of the grid conductor losses associated with multiple-connected unit cells shows the disastrous effect that the grid header resistance can have on the performance of a solar cell. The results indicate that the use of a tapered header conductor to decrease the metal coverage may actually worsen cell performance. Copyright © 1978 by The Institute of Electrical and Electronics Engineers, Inc.


Electrical and Computer Engineering

International Standard Serial Number (ISSN)

1557-9646; 0018-9383

Document Type

Article - Journal

Document Version


File Type





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Publication Date

01 Jan 1978