Test Generation for Combinational Logic Circuits using Information Theory
Application of Probability and Information Theory to Test Pattern Generation for Combinational Logic Circuits is Investigated. It is Verified that Choosing the Input Probability to Maximize the Output Information Reduced to a Minimum the Number of Random Patterns to Be Generated to Detect All the Faults in the Circuit. This Result is Tested on Three Examples using a Logic Simulator. the Simulator Was Implemented using a TRS-80 Color Computer with 16K Memory, and the Use of Microcomputers in Fault Detection is Discussed. This Work Considers Only Combinational Logic Circuits and Single Stuck-At Type Faults. © 1986.
P. D. Stigall and Y. M. Erten, "Test Generation for Combinational Logic Circuits using Information Theory," Computers and Electrical Engineering, vol. 12, no. 1 thru 2, pp. 51 - 63, Elsevier, Jan 1986.
The definitive version is available at https://doi.org/10.1016/0045-7906(86)90019-4
Electrical and Computer Engineering
International Standard Serial Number (ISSN)
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01 Jan 1986