Abstract
This paper presents an impedance model of on-chip power distribution network (PDN), which is an efficient criterion for estimating simultaneous switching noises (SSNs) on 3-D integrated circuit (IC). The impedance of on-chip PDN, including the effect of silicon substrate, is accurately modeled based on partial element equivalent circuit (PEEC) and layered Green's function (LGF). The equivalent circuit model of PDN is extracted based on the physical dimensions and electrical material characteristic of PDN at first. And then the LGF is used to consider the effect of silicon substrate for improving the accuracy of on-chip PDN impedance model. The effectiveness of proposed model has been validated by full wave simulation. The high order resonance of PDN impedance can also be accurately predicted.
Recommended Citation
C. Li et al., "Peec-Based On-Chip Pdn Impedance Modeling using Layered Green's Function," 2022 IEEE International Symposium on Electromagnetic Compatibility and Signal/Power Integrity, EMCSI 2022, pp. 164 - 168, Institute of Electrical and Electronics Engineers, Jan 2022.
The definitive version is available at https://doi.org/10.1109/EMCSI39492.2022.9889515
Department(s)
Electrical and Computer Engineering
Keywords and Phrases
impedance modeling; LGF; PDN; PEEC; silicon substrate; SSNs
International Standard Book Number (ISBN)
978-166540929-2
Document Type
Article - Conference proceedings
Document Version
Final Version
File Type
text
Language(s)
English
Rights
© 2023 Institute of Electrical and Electronics Engineers, All rights reserved.
Publication Date
01 Jan 2022
Comments
National Science Foundation, Grant IIP-1916535