Title

Novel Area-Efficient Null Convention Logic based on CMOS and Gate Diffusion Input (GDI) Hybrid

Abstract

Null convention logic (NCL) is a promising delay insensitive paradigm for constructing asynchronous circuits. Traditionally, NCL circuits are implemented utilizing complementary metal oxide semiconductor (CMOS) technology that has large area overhead. To address this issue, a HYBRID methodology is introduced for realizing NCL circuits in this paper. The proposed approach utilizes both CMOS and gate diffusion input (GDI) techniques to significantly reduce the area. Compared with the conventional static CMOS NCL counterpart, the HYBRID implementation of an NCL up counter demonstrate an average of 10% reduction in the transistor count.

Department(s)

Electrical and Computer Engineering

Keywords and Phrases

Gate Diffusion Input; HYBRID Implementation; Null Convention Logic; Ripple Carry Adder

International Standard Serial Number (ISSN)

1598-1657

Document Type

Article - Journal

Document Version

Citation

File Type

text

Language(s)

Mandarin

Rights

© 2020 Institute of Electronics Engineers of Korea, All rights reserved.

Publication Date

01 Feb 2020

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