Title

Improved Target Impedance Concept with Jitter Specification

Abstract

In this article, an improved target impedance concept directly correlating circuit output jitter with power distribution network (PDN) R-L-C parameters is proposed. A systematic procedure to develop the target impedance curves is formulated and developed for common CMOS buffer circuits. The relationship between output jitter and PDN R-L-C parameters is analytically derived by evaluating the time domain voltage ripple to jitter transfer relationship along with the relationship between time domain voltage ripple and PDN R-L-C parameters. Given the transient integrated circuit switching current and the jitter specification, multiple target impedance curves can be defined for a specific circuit. The jitter and PDN R-L-C analytical correlations are validated through HSPICE simulation. The application of the proposed target impedance concept with jitter specification is also demonstrated via simulation.

Department(s)

Electrical and Computer Engineering

Research Center/Lab(s)

Intelligent Systems Center

Comments

National Science Foundation, Grant IIP-1916535

Keywords and Phrases

Buffer; Jitter; Jitter Transfer Function; Power Supply Induced Jitter; Target Impedance

International Standard Serial Number (ISSN)

0018-9375; 1558-187X

Document Type

Article - Journal

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 2020 Elsevier, All rights reserved.

Publication Date

05 Jun 2020

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