Improved Target Impedance Concept with Jitter Specification
In this article, an improved target impedance concept directly correlating circuit output jitter with power distribution network (PDN) R-L-C parameters is proposed. A systematic procedure to develop the target impedance curves is formulated and developed for common CMOS buffer circuits. The relationship between output jitter and PDN R-L-C parameters is analytically derived by evaluating the time domain voltage ripple to jitter transfer relationship along with the relationship between time domain voltage ripple and PDN R-L-C parameters. Given the transient integrated circuit switching current and the jitter specification, multiple target impedance curves can be defined for a specific circuit. The jitter and PDN R-L-C analytical correlations are validated through HSPICE simulation. The application of the proposed target impedance concept with jitter specification is also demonstrated via simulation.
Y. Sun et al., "Improved Target Impedance Concept with Jitter Specification," IEEE Transactions on Electromagnetic Compatibility, vol. 62, no. 4, pp. 1534-1545, Elsevier, Jun 2020.
The definitive version is available at https://doi.org/10.1109/TEMC.2020.2996430
Electrical and Computer Engineering
Keywords and Phrases
Buffer; Jitter; Jitter Transfer Function; Power Supply Induced Jitter; Target Impedance
International Standard Serial Number (ISSN)
Article - Journal
© 2020 Elsevier, All rights reserved.
05 Jun 2020