A Systematic Method to Characterize the Soft-Failure Susceptibility of the I/Os on an Integrated Circuit Due to Electrostatic Discharge


In this paper, we present a methodology to characterize the I/O pins of a logic IC such as an application processor or ASIC with respect to soft-failure susceptibility due to electrostatic discharge. With the IC in a functional system, variable stress pulses are injected while the interface under test operates in real-world use cases. This test methodology enables the extraction of the IC behavior during ESD-like stress on a pin-by-pin basis. This characterization is intended to be performed during the validation stages of component development, making it possible to provide system developers with valuable information about potential modes of failure. This early detection of potential soft errors and their sensitivities can then be used to design for soft-failure robustness from the very beginning of system hardware and software design.


Electrical and Computer Engineering

Research Center/Lab(s)

Electromagnetic Compatibility (EMC) Laboratory


This work was supported in part by the National Science Foundation under Grant 1440110.

Keywords and Phrases

Electrostatic Interference; Fault Tolerance; Immunity Testing; Integrated Circuit Reliability; System-On-Chip

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Document Type

Article - Journal

Document Version


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Publication Date

01 Feb 2020