On-Chip Linear Voltage Regulator Module (VRM) Effect on Power Distribution Network (PDN) Noise and Jitter at High-Speed Output Buffer


In this paper, the reduction of power distribution network noise and jitter at high-speed output buffer by using on-chip linear voltage regulator module circuit is introduced and analyzed. The transient response of typical on-chip linear VRM circuit is analyzed in power gating condition. When the on-chip linear VRM circuit is inserted between on-chip PDN and operating high-speed output buffers, the on-chip PDN noise and jitter at output buffer are significantly reduced. The larger on-chip decoupling capacitor leads to the lower PDN noise generated by on-chip linear VRM circuit. The on-chip linear VRM also reduces the impact of the aggressor buffer to the victim buffer in different PDN, resulting in the improved performance of the victim buffer. Reduction of PDN noise and jitter at output buffer using on-chip linear VRM are validated based on SPICE simulation with 110 nm CMOS technology library.


Electrical and Computer Engineering

Research Center/Lab(s)

Electromagnetic Compatibility (EMC) Laboratory


National Science Foundation (U.S.)


This material is based upon work supported by the National Science Foundation under Grant No. IIP-1440110.

Keywords and Phrases

CMOS integrated circuits; Electric network analysis; Jitter; SPICE; Voltage regulators; CMOS technology; Linear voltage regulators; On-chip Decoupling capacitors; PDN noise; Power distribution network; Power gatings; SPICE simulations; Victim buffer; Integrated circuit interconnects; On-chip linear voltage regulator module (VRM); Power distribution network (PDN)

International Standard Serial Number (ISSN)

2162-2264; 2162-2272

Document Type

Article - Journal

Document Version


File Type





© 2015 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Publication Date

01 Aug 2015