Repairability Evaluation of Embedded Multiple Region DRAMs
Abstract
This paper presents a method to evaluate the repairability of embedded redundant DRAMS with multiple regions. An architecture-oriented repairability evaluation method is proposed. This identifies the bounds on the repairability that provides the best and worst case repair success rate of a redundant DRAM architecture partitioned into multiple regions. A comparative study is conducted by using the proposed method to evaluate the repairabilities of different architectures. The novelty is that the proposed method can be driven without suffering from the NP-completeness of conventional repairability evaluation methods that rely on exhaustive and exponential search due to their being algorithm-oriented unless a heuristic is provided at a high cost of overhead. The repairability bounds of symmetric single subregion, multiple subregion DRAMS are investigated as criteria since the complexity of their repair algorithms drives algorithm-oriented repairability analysis methods impractical. Ultimately, the proposed method will establish a practical and cost-effective approach to assuring the yield and repairability of ultra high density embedded DRAM cores on System-on-Chip.
Recommended Citation
Y. Chang et al., "Repairability Evaluation of Embedded Multiple Region DRAMs," Proceedings of the 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (2002, Vancouver, Canada), pp. 428 - 436, IEEE Computer Society, Nov 2002.
The definitive version is available at https://doi.org/10.1109/DFTVS.2002.1173541
Meeting Name
17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (2002: Nov. 6-8, Vancouver, Canada)
Department(s)
Electrical and Computer Engineering
Keywords and Phrases
Algorithms; Application Specific Integrated Circuits; Computational Complexity; Computer Science; Cost Benefit Analysis; Cost Effectiveness; Costs; Defects; Design For Testability; Dynamic Random Access Storage; Fabrication; Fault Tolerance; Heuristic Algorithms; Memory Architecture; Microprocessor Chips; Repair; Semiconductor Device Manufacture; Semiconductor Devices; Semiconductor Storage; System-on-Chip; Algorithm Design And Analysis; Comparative Studies; Cost-Effective Approach; Evaluation Methods; Multiple Sub-Regions; Random Access Memory; Semiconductor Memory; System On A Chip; Heuristic Methods; NP-Complete Problem
International Standard Book Number (ISBN)
769518311
International Standard Serial Number (ISSN)
1550-5774
Document Type
Article - Conference proceedings
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2002 IEEE Computer Society, All rights reserved.
Publication Date
01 Nov 2002
