Post-Configuration Repair Strategy for Asynchronous Nanowire Crossbar System
The recently proposed asynchronous nanowire crossbar architecture is envisioned to enhance the manufacturability and robustness of nanowire crossbar-based configurable digital circuits by removing various timing-related failure modes. Even though the proposed clock-free nanowire crossbar architecture has numerous technical merits over its clocked counterparts, it is still subject to high defect rates inherently induced by the nondeterministic nanoscale assembly of nanowire crossbars. To address this issue, a novel post-configuration repair strategy specific to the asynchronous nanowire crossbar architecture has been proposed. The proposed repair strategy is to selectively test highly defect-prone ON-state programmed crosspoints and reconfigure the given logic function to circumvent the ON-crosspoints tested as faulty by utilizing redundant rows/columns.
J. Wu et al., "Post-Configuration Repair Strategy for Asynchronous Nanowire Crossbar System," Proceedings of the IEEE 55th International Midwest Symposium on Circuits and Systems (2012, Boise, ID), pp. 174-177, Institute of Electrical and Electronics Engineers (IEEE), Aug 2012.
The definitive version is available at https://doi.org/10.1109/MWSCAS.2012.6291985
IEEE 55th International Midwest Symposium on Circuits and Systems: MWSCAS (2012: Aug. 5-8, Boise, ID)
Electrical and Computer Engineering
Keywords and Phrases
Crossbar Architecture; Defect Rate; Functional Testing; Logic Functions; Manufacturability; Nanoscale Assemblies; Repair Strategy; Clocks; Defects; Fault Tolerance; Nanowires; Redundancy; Repair; Asynchronous Sequential Logic; Asynchronous Nanowire Crossbar Architecture; Defect & Fault-Tolerance; Post-Configuration Repair
International Standard Book Number (ISBN)
International Standard Serial Number (ISSN)
Article - Conference proceedings
© 2012 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
01 Aug 2012