Hybrid GDI-NCL for Area/Power Reduction
Abstract
Null Convection Logic is a well-known paradigm for designing asynchronous logic circuits. The conventional CMOS-based NCL designs suffers larger area overhead and power consumption. A low power design technique called Gate Diffusion Input (GDI) has been adopted to overcome this limitation. In GDI technology, voltage swing exhibits significant voltage drop across the circuit. Therefore, not suitable for designing large combinational circuits. A novel HYBRID (CMOS+GDI) design is proposed in this work to efficiently address this issue. The HYBRID design utilizes both CMOS and GDI technology to reduce the number of transistor and power dissipation when compared to CMOS NCL circuits. The proposed approach is implemented in NCL Ripple Carry Adder (RCA) and simulated in Cadence Virtuoso for verification.
Recommended Citation
P. Metku et al., "Hybrid GDI-NCL for Area/Power Reduction," Proceedings of the International SoC Design Conference (2016, Jeju, South Korea), pp. 93 - 94, Institute of Electrical and Electronics Engineers (IEEE), Oct 2016.
The definitive version is available at https://doi.org/10.1109/ISOCC.2016.7799749
Meeting Name
International SoC Design Conference: ISOCC (2016: Oct. 23-26, Jeju, South Korea)
Department(s)
Electrical and Computer Engineering
Keywords and Phrases
CMOS Integrated Circuits; Electric Power Supplies to Apparatus; Integrated Circuit Design; Logic Design; Area Overhead; Asynchronous Logic Circuits; Hybrid Design; Low Power Design Technique; Ripple Carry Adders; Voltage Drop; Voltage Swings; Computer Circuits
International Standard Book Number (ISBN)
978-1509032198; 978-1509032204
Document Type
Article - Conference proceedings
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2016 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
Publication Date
01 Oct 2016
