Environmental Based Characterization of SoC for Stratified Testing


This paper proposes a novel environmental-based method for evaluating the good yield rate (GYR) of Systems-on-Chip (SoC) during fabrication. Testing and yield evaluation at high confidence are two of the most critical issues for the technological success of SoC. Since a SoC is designed and assembled using deeply embedded Intellectual Property (IP) cores on a single chip, then at fabrication, it is not possible to rely on conventional testing and yield evaluation methods because there is no a-priori information or data available on the yield of the fabricated IPs due to the different integration processes of the cores. This is radically different from previous technologies in which the known-good-yield of ASIC or MCM chips for example is extracted from physical-level information. The proposed method relies on different aspects of fabrication (which are quantified by the so-called Environmental Parameters (EP)). EPs which could be highly correlated to the yield, are analyzed using a comprehensive statistical method to improve the accuracy of the estimated yield of the SoC as well as for directing the test process. Numerical simulation results are provided to show that the proposed method significantly improves the confidence interval of the estimated yield when compared to conventional random testing.

Meeting Name

20th IEEE Instrumentation and Measurement Technology Conference: IMTC (2003: May 20-22, Vail, CO)


Electrical and Computer Engineering

Keywords and Phrases

Computer Simulation; Environmental Testing; Intellectual Property; Systems Analysis; VLSI Circuits; Application Specific Integrated Circuits; Assembly; Computer Integrated Manufacturing; Computer Science; Electric Network Analysis; Fabrication; Integrated Circuit Testing; Integrated Circuits; Integration Testing; Manufacture; Microprocessor Chips; Numerical Methods; Programmable Logic Controllers; Statistical Methods; Environmental Parameter (EP); System-on-Chip; Confidence Interval; Conventional Testing; Integration Process; Intellectual Property Cores; Stratified Testing; System Testing; Yield Estimation

International Standard Book Number (ISBN)


International Standard Serial Number (ISSN)


Document Type

Article - Conference proceedings

Document Version


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© 2003 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Publication Date

01 May 2003