Efficient Post-Configuration Testing of an Asynchronous Nanowire Crossbar System for Reliability
The recently proposed asynchronous nanowire crossbar architecture is envisioned to enhance the manufacturability and robustness of nanowire crossbar-based configurable digital circuits by removing various timing-related failure modes. Even though the proposed clock-free nanowire crossbar architecture has numerous technical merits over its clocked counterparts, it is still subject to high defect rates inherently induced by the non-deterministic nanoscale assembly of nanowire crossbars. In order to address this issue, a novel functional testing scheme has been proposed to validate threshold gates configured on programmable gate macro blocks (PGMB). The proposed approach selectively tests the crosspoints programmed as ON-state using test vectors tailored to the given threshold gate macro and its functionality. Therefore high-fault coverage can be achieved at significantly reduced test overhead. Also, numerous replacement and reconfiguration schemes have been proposed based on the proposed functional testing scheme to repair configured PGMBs that are partially faulty by locating incorrectly programmed crosspoints and replacing them with defect-free spares. Specific figures of merit have also been coined to quantify the performance of the proposed testing and reconfiguration algorithms. These findings have been extensively validated by a series of parametric simulations.
J. Lee et al., "Efficient Post-Configuration Testing of an Asynchronous Nanowire Crossbar System for Reliability," IET Computers and Digital Techniques, vol. 6, no. 4, pp. 214 - 222, Institution of Engineering and Technology (IEE), Jul 2012.
The definitive version is available at https://doi.org/10.1049/iet-cdt.2011.0025
Electrical and Computer Engineering
Keywords and Phrases
Crossbar Architecture; Defect Rate; Defect-Free; Figures of Merits; Functional Testing; Macro Block; Manufacturability; Nanoscale Assemblies; Parametric Simulations; Programmable Gate; Reconfiguration Algorithm; Reconfiguration Schemes; Test Vectors; Threshold Gates; Asynchronous Sequential Logic; Clocks; Defects; Resonant Tunneling; Threshold Logic; Nanowires
International Standard Serial Number (ISSN)
Article - Journal
© 2012 Institution of Engineering and Technology (IEE), All rights reserved.
01 Jul 2012