Design and Evaluation of Side Channel Attack Resistant Asynchronous AES Round Function


A novel Asynchronous AES Round Function design is proposed in this paper, which offers increased Side-Channel Attack (SCA) resistance by combining the advantages of dual rail encoding and clock free operation. The design is based on a Delay Insensitive (DI) logic paradigm known as Null Convention Logic. By reducing switching activity and thereby Signal-to-Noise (SNR) ratio, the proposed design leaks far less side channel information than traditional approaches and this feature boosts SCA resistance of this approach. Functional verification and WASSO analysis simulations were carried out on both synchronous approach and the proposed NCL based approach using Xilinx simulation tools to validate the claims related to benefits of employing this novel dual rail design approach.

Meeting Name

IEEE 55th International Midwest Symposium on Circuits and Systems: MWSCAS (2012: Aug. 5-8, Boise, ID)


Electrical and Computer Engineering

Keywords and Phrases

AES Round Function; Design Approaches; Dual Rail; Dual Rail Encoding; Functional Verification; Logic Paradigm; Null Convention Logic; Side Channel Attack; Side-Channel Information; Signal to Noise; Switching Activities; Design; Signal to Noise Ratio

International Standard Book Number (ISBN)

978-1467325264; 978-1467325271

International Standard Serial Number (ISSN)

1548-3746; 1558-3899

Document Type

Article - Conference proceedings

Document Version


File Type





© 2012 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Publication Date

01 Aug 2012