Algorithmic GPGPU Memory Optimization


The performance of General-Purpose computation on Graphics Processing Units (GPGPU) is heavily dependent on the memory access behavior. This sensitivity is due to a combination of the underlying Massively Parallel Processing (MPP) execution model present on GPUs and the lack of architectural support to handle irregular memory access patterns. Application performance can be significantly improved by applying memory-access-pattern-aware optimizations that can exploit knowledge of the characteristics of each access pattern. In this paper, we present an algorithmic methodology to semi-automatically find the best mapping of memory accesses present in serial loop nest to underlying data-parallel architectures based on a comprehensive static memory access pattern analysis. To that end we present a simple, yet powerful, mathematical model that captures all memory access pattern information present in serial data-parallel loop nests. We then show how this model is used in practice to select the most appropriate memory space for data and to search for an appropriate thread mapping and work group size from a large design space. To evaluate the effectiveness of our methodology, we report on execution speedup using selected benchmark kernels that cover a wide range of memory access patterns commonly found in GPGPU workloads. Our experimental results are reported using the industry standard heterogeneous programming language, OpenCL, targeting the NVIDIA GT200 architecture.


Electrical and Computer Engineering

Keywords and Phrases

Algorithms; Computer Graphics; Mapping; Mathematical Models; Parallel Architectures; Data-Parallel Architectures; General-Purpose Computations; GPGPU; GPU Computing; Heterogeneous Programming; Massively Parallel Processing; Memory Access Pattern; Memory Optimization; Program Processors; GPU Memory Optimization; Thread Mapping

International Standard Serial Number (ISSN)

1598-1657; 2233-4866

Document Type

Article - Journal

Document Version


File Type





© 2014 Institute of Electronics Engineers of Korea, All rights reserved.

Publication Date

01 Aug 2014