Multi-level, Memory-based Logic using CMOS Technology
Abstract
A memory-based approach is described for performing basic logic gate functions. CMOS transistors are used in a non-traditional way for multi-level operations and memory manipulation. Sense amplifier circuits drive an array of pass amplifiers in which memory values are set by reference connections. The combination of multi-level architectures and matrix algebra principles can create flexible, modular systems using standard fabrication methods. Logic gate functions of AND, OR, NAND, and NOR are implemented in quaternary, memory-based architectures. The circuit layouts and functional simulations are given and are compared to those of similar binary circuits. Experimental performance of a hardware AND chip is also demonstrated. The approach requires more chip area for basic logic gates, but it grows increasingly efficient for more complex systems through hardware reuse. The benefits and feasibility of more complex applications are discussed.
Recommended Citation
I. P. Dugganapally et al., "Multi-level, Memory-based Logic using CMOS Technology," Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI (2014, Tampa, FL), pp. 584 - 589, IEEE Computer Society, Jan 2014.
The definitive version is available at https://doi.org/10.1109/ISVLSI.2014.91
Meeting Name
2014 IEEE Computer Society Annual Symposium on VLSI, ISVLSI (2014: Jul. 9-11, Tampa, FL)
Department(s)
Electrical and Computer Engineering
International Standard Book Number (ISBN)
978-1479937653; 978-1479937639
International Standard Serial Number (ISSN)
2159-3469
Document Type
Article - Conference proceedings
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2014 IEEE Computer Society, All rights reserved.
Publication Date
01 Jan 2014
