Continuous-Time Optimization of Gate Timing for Synchronous Rectification
Synchronous rectifiers, which use a controlled MOSFET in place of a standard p-n or Schottky rectifier, are an important technology for low-voltage power converters. Conventional control techniques for synchronous rectification are often very conservative, however, leaving room for improvement. This paper presents a method for monitoring current flow to adaptively optimize the relative timing of two gate signals for a buck converter with synchronous rectification. Theoretical development is given, along with experimental results for two low-voltage converters.
J. W. Kimball and P. T. Krein, "Continuous-Time Optimization of Gate Timing for Synchronous Rectification," Proceedings of the 39th Midwest Symposium on Circuits and Systems (1996, Ames, IA), vol. 3, pp. 1015-1018, Institute of Electrical and Electronics Engineers (IEEE), Aug 1996.
The definitive version is available at https://doi.org/10.1109/MWSCAS.1996.592895
39th Midwest Symposium on Circuits and Systems (1996: Aug. 18-21, Ames, IA)
Electrical and Computer Engineering
University of Illinois at Urbana-Champaign. Power Affiliates Program
Keywords and Phrases
Electric Current Control; Gates (Transistor); MOSFET Devices; Optimization; Power Converters; Low Voltage Power Converters; Synchronous Rectifiers; Electric Rectifiers; Timing; Rectifiers; Pulse Width Modulation; MOSFET Circuits; Thyristors; Power MOSFET; Buck Converters; Adaptive Algorithm; Voltage; Switches; Power Convertors; Rectification; Optimisation; Continuous Time Systems; Timing
International Standard Book Number (ISBN)
Article - Conference proceedings
© 1996 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
01 Aug 1996