Modeling of On-Chip Power Distribution Network
Because of its nature, the approach to an on-chip power distribution network (PDN) is quite different from that of an off-chip PDN. In this chapter, on-chip PDN modeling is discussed. We begin Section 5.2 by modeling on-chip capacitors. Section 5.3 extracts the electrical characteristics of the on-chip wires forming the PDN. Section 5.4 is devoted to an off-chip PDN incorporating PCB and vias. Section 5.5 investigates the power supply induced jitter. The signal output is contaminated by the supply voltage fluctuation; the trends are analyzed at the transistor level and physically understood.
C. Hwang et al., "Modeling of On-Chip Power Distribution Network," Noise Coupling in System-on-Chip, pp. 93 - 138, CRC Press, Dec 2017.
Electrical and Computer Engineering
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01 Dec 2017