A 6.4Gbps On-Chip Eye Opening Monitor Circuit for Signal Integrity Analysis of High Speed Channel
In this paper, an on-chip eye opening monitor circuit has been proposed with 4ps time and 4mv voltage resolutions for analyzing signal integrity of on-chip high speed channel. The proposed eye opening monitor circuit can detect the maximum 6.4Gbps data rate and give eye diagrams depending on on-chip high speed channel conditions. The performance of the proposed eye opening monitor circuit was verified by using a general spice simulations and showed the variations of eye diagram of 6.4 Gbps random data when on-die terminations of on-chip high speed channel was changed from 50 ohm to 80 ohm.
M. Shin and J. Shim and J. Kim and J. Pak and C. Hwang and C. Yoon and J. Kim and H. Kim and K. Park and Y. Kim, "A 6.4Gbps On-Chip Eye Opening Monitor Circuit for Signal Integrity Analysis of High Speed Channel," Proceedings of the IEEE International Symposium on Electromagnetic Compatibility (2008, Detroit, MI), Institute of Electrical and Electronics Engineers (IEEE), Aug 2008.
The definitive version is available at https://doi.org/10.1109/ISEMC.2008.4652099
IEEE International Symposium on Electromagnetic Compatibility, EMC 2008 (2008: Aug. 18-22, Detroit, MI)
Electrical and Computer Engineering
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22 Aug 2008