Modeling and Analysis of a Power Distribution Network in TSV-Based 3-D Memory IC Including P/G TSVs, On-Chip Decoupling Capacitors, and Silicon Substrate Effects
In this paper, we propose a model for 3-D stacked on-chip power distribution networks (PDNs) in through silicon via (TSV)-based 3-D memory ICs that includes the effects of power/ground TSVs (P/G TSVs), on-chip decoupling capacitors (on-chip decaps), and the silicon substrate. In the modeling procedure of 3-D stacked on-chip PDNs, the distributed RLGC-lumped model of an on-chip PDN, including the effects of the on-chip decaps and silicon substrate, is proposed. Additionally, the RLGC-lumped model of a P/G TSV pair is introduced. The proposed model of the 3-D stacked on-chip PDN combines the proposed models of on-chip PDNs with the models of P/G TSV pairs in a hierarchical order with a segmentation method. The proposed models of the on-chip PDN and 3-D stacked on-chip PDN are successfully validated by simulations and measurements up to 20 GHz. Additionally, with these models, the impedances of the 3-D stacked on-chip PDNs are analyzed with respect to the variations in the number of P/G TSV pairs, the capacitance of on-chip decaps, and the height of an interlayer dielectric layer between the on-chip PDN and silicon substrate. These variations critically affect the impedance of the 3-D stacked on-chip PDN by changing the capacitance and inductance of the PDN.
K. Kim and C. Hwang and K. Koo and J. Cho and H. Kim and J. Kim and J. Lee and H. Lee and K. Park and J. Pak, "Modeling and Analysis of a Power Distribution Network in TSV-Based 3-D Memory IC Including P/G TSVs, On-Chip Decoupling Capacitors, and Silicon Substrate Effects," IEEE Transactions on Components, Packaging, and Manufacturing Technology, vol. 2, no. 12, pp. 2057-2070, Institute of Electrical and Electronics Engineers (IEEE), Jan 2012.
The definitive version is available at https://doi.org/10.1109/TCPMT.2012.2214482
Electrical and Computer Engineering
Keywords and Phrases
3-D Stacked On-Chip Power Distribution Network (PDN); On-Chip Decoupling Capacitor (Decap); On-Chip PDN; PDN Impedance; Power/ground (P/G) TSV; Silicon Substrate; Through Silicon Via (TSV)-Based 3-D ICs
International Standard Serial Number (ISSN)
Article - Journal
© 2012 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
01 Jan 2012