Simple D Flip-Flop Behavioral Model of ESD Immunity for Use in the ISO 10605 Standard


As the ESD stress is becoming more and more important for integrated circuits (ICs), the ability to predict IC failures becomes critical. In this paper, an 18 MHz D flip-flop IC is characterized and its behavioral model is presented. The resulting IC model is validated in the setup according to the ISO 10605 standard. A complete model of the setup combining the IC behavioral model and the passive parts of the setup is built to estimate the failure prediction accuracy in a totally simulated environment. The results show that the model can predict the triggering level with the error of less than 20%.

Meeting Name

2014 IEEE International Symposium on Electromagnetic Compatibility (2014: Aug. 3-8, Raleigh, NC)


Electrical and Computer Engineering

Research Center/Lab(s)

Electromagnetic Compatibility (EMC) Laboratory

Keywords and Phrases

Behavioral research; Electromagnetic compatibility; Electrostatic devices; Electrostatic discharge; Forecasting; Behavioral model; D flip flops; ESD stress; Failure prediction; IC-Models; Integrated circuits (ICs); Simulated environment; Flip flop circuits

International Standard Serial Number (ISSN)


Document Type

Article - Conference proceedings

Document Version


File Type





© 2014 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Publication Date

01 Sep 2014