Extraction of the Parameters of the Coupling Capacitance Hysteresis Cycle for TSV Transient Modeling
The paper deals with the extraction, from the measurement, of the parameters needed to identify in time domain the hysteretic behavior of the coupling capacitance of through silicon via (TSV). The algorithm is developed in such a way that the equivalent capacitance model can be implemented into standard circuit simulators. Results showing the effect of the hysteresis on the crosstalk among TSV and IC active devices are shown and discussed.
S. Piersanti et al., "Extraction of the Parameters of the Coupling Capacitance Hysteresis Cycle for TSV Transient Modeling," IEEE International Symposium on Electromagnetic Compatibility (2016, Ottawa, Canada), pp. 406 - 411, Institute of Electrical and Electronics Engineers (IEEE), Jul 2016.
The definitive version is available at https://doi.org/10.1109/ISEMC.2016.7571682
2016 IEEE International Symposium on Electromagnetic Compatibility (2016: Jul. 25-29, Ottawa, Canada)
Electrical and Computer Engineering
Center for High Performance Computing Research
Second Research Center/Lab
Electromagnetic Compatibility (EMC) Laboratory
Keywords and Phrases
Capacitance; Circuit simulation; Electromagnetic compatibility; Electronics packaging; Equivalent circuits; Extraction; Hysteresis; Integrated circuit interconnects; Integrated circuit manufacture; Reconfigurable hardware; Active devices; Dielectric hysteresis; Equivalent circuit model; Nonlinear effect; Signal Integrity; Through silicon vias; Time domain; Three dimensional integrated circuits
International Standard Book Number (ISBN)
International Standard Serial Number (ISSN)
Article - Conference proceedings
© 2016 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
01 Jul 2016