The engineering of the power delivery network is becoming a fundamental issue in the design of high speed digital systems on PCB's. In fact, providing the required power to the different IC's at the specified noisefree voltage levels allows a correct functioning of the overall PCB systems. More over, the ongoing trend of replacing active devices with peripherally located I/O and PWR/GND pins with areally located I/O and PWR/GND pins (BGA packaged) increases the complexity of the models, when power delivery issues need to be studied in a larger contest, such as the overall PCB's. The employment of the powerful, but simple, concept of the segmentation method allows investigation of the power delivery network of the PCB systems in two fundamental stages. During the first stage, a small cut out of the board corresponding to the BGA footprint is modelled with a 3D full wave simulation tool. During the second stage the equivalent impedance network representation corresponding to this cut out is combined, by means of the segmentation method [1-5], with larger pieces of a board, whose network representations can be extracted from the closed form expression of the cavity model approach [6-9].

Meeting Name

IEEE International Symposium on Electromagnetic Compatibility (2005: Aug. 8-12, Chicago, IL)


Electrical and Computer Engineering

Research Center/Lab(s)

Electromagnetic Compatibility (EMC) Laboratory

Keywords and Phrases

Ball Grid Array (BGA) Footprints; Cavity Mode Approaches; Equivalent Network Representation; Power Integrity; Segmentation Methods; Digital Devices; Integrated Circuits; Networks (Circuits); Printed Circuit Boards; Speed Control; Voltage Control; Power Electronics; Ball Grid Array (BGA) Footprint; Cavity Mode Approach; Equivalent Network Representation; Power Integrity; Segmentation Method

International Standard Book Number (ISBN)


International Standard Serial Number (ISSN)

2158-110X; 2158-1118

Document Type

Article - Conference proceedings

Document Version

Final Version

File Type





© 2005 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Publication Date

01 Aug 2005