DC power bus design is critical in meeting signal integrity (SI) and electromagnetic compatibility (EMC) requirements. A suitable modeling tool is beneficial to evaluate power bus design and develop design guidelines. This paper discusses difficulties met in evaluating the power distribution design on a dual inline memory module (DIMM) board, such as a power bus with arbitrary shape, parasitic inductance associated with vias, and so on. Moreover, some solutions are given in this paper. A simple cavity model with a segmentation method was employed to model a power bus with irregular shapes. The partial element equivalent circuit (PEEC) technique was applied to model the electrical properties of a high-speed via interconnect. For each proposed approach, the difference between the estimates and measurements demonstrates the application of these approaches in the DIMM DC power distribution analysis and design.
J. Mao et al., "Memory DIMM DC Power Distribution Analysis and Design," Proceedings of the IEEE International Symposium on Electromagnetic Compatibility (2003, Boston, MA), vol. 2, pp. 597 - 602, Institute of Electrical and Electronics Engineers (IEEE), Aug 2003.
The definitive version is available at https://doi.org/10.1109/ISEMC.2003.1236670
IEEE International Symposium on Electromagnetic Compatibility (2003: Aug. 18-22, Boston, MA)
Electrical and Computer Engineering
Electromagnetic Compatibility (EMC) Laboratory
Keywords and Phrases
DC Power Bus Design; DC Power Distribution; DIMM Board; PEEC Technique; Cavity Model; Dual Inline Memory Module; Electromagnetic Compatibility; Equivalent Circuits; High-Speed Via Interconnect; Integrated Circuit Interconnections; Partial Element Equivalent Circuit; Power Distribution Design; Printed Circuit Design; Segmentation Method; Signal Integrity; Simultaneous Switching Noise; DC Power; PEEC; Computer Simulation; Electric Network Analysis; Electric Power Supplies To Apparatus; Inductance; Interconnection Networks; Printed Circuit Boards; Direct Current Power Distribution; High-Speed Via Interconnect; Partial Element Equivalent Circuit Technique; Electric Network Synthesis
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Article - Conference proceedings
© 2003 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
01 Aug 2003