I DDQ (Defect Detection by Quiescent power supply current measurement), or current testing, has emerged in the last few years as an effective technique for detecting certain classes of faults in high-density ICs. In this paper, a testable design that enhances the I DDQ testability of static random access memories (SRAMs) for off-line testing as proposed. To achieve high accuracy and a test speed approaching the system operational speed, the memory is partitioned for comparison of I DDQ values. Parallel write/read operations are used to activate possible faults, while quiescent power supply currents from two blocks are compared


Electrical and Computer Engineering

Keywords and Phrases

SRAM; SRAM Chips; Accuracy; Bipartite Differential I/DDQ/ Testable Static RAM Design; Current Testing; Defect Detection; Fault Activation; Fault Diagnosis; Fault Location; High-Density IC Fault Detection; Integrated Circuit Testing; Memory Partitioning; Off-Line Testing; Parallel Write/Read Operations; Quiescent Power Supply Current Measurement; Static Random Access Memories; System Operational Speed; Test Speed; Testability

Document Type

Article - Conference proceedings

Document Version

Final Version

File Type





© 1995 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Publication Date

01 Jan 1995