Due to the absence of a global clock and presence of more state holding elements that synchronize the control and data paths, conventional automatic test pattern generation (ATPG) algorithms would fail when applied to asynchronous circuits, leading to poor fault coverage. This paper focuses on design for test (DFT) techniques aimed at making asynchronous NCL designs testable using existing DFT CAD tools with reasonable gate overhead, by enhancing controllability of feedback nets and observability for fault sites that are flagged unobservable. The proposed approach performs scan and test points insertion on NCL designs using custom ATPG library. The approach has been automated, which is essential for large systems; and are fully compatible with industry standard tools.
S. Kakarla and W. K. Al-Assadi, "Testing of Asynchronous NULL Conventional Logic (NCL) Circuits," Proceedings of the IEEE Region 5 Conference, 2008, Institute of Electrical and Electronics Engineers (IEEE), Apr 2008.
The definitive version is available at https://doi.org/10.1109/TPSD.2008.4562764
IEEE Region 5 Conference, 2008
Electrical and Computer Engineering
National Science Foundation (U.S.)
Keywords and Phrases
Asynchronous Circuits; Automatic Test Pattern Generation; Design for Testability; Integrated Circuit Testing; Logic CAD
Article - Conference proceedings
© 2008 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
01 Apr 2008