Characterizing Traction-Separation Relations of TSV/SI Interfaces by Nanoindentation
Through-silicon-vias (TSV) are the copper interconnects that are used connect integrated three dimensional microelectronics devices which consist of multiple silicon layers. Previous research has focused on various modeling techniques for determining thermo-mechanical stresses, extrusion and stress intensity factors associated with interfacial delamination. However, predictions based on such analyses all require the characterization of interfacial properties, which has been scarce. The objective of this work is to develop an experimental technique for the direct measurement of interfacial properties between a TSV and its silicon matrix. Traction-separation relations can be used to represent the adhesive interactions associated with bimaterial interfaces. In this paper, a direct method is proposed to determine the mode-II traction separation relation for the interface between silicon and a copper through-silicon-via (TSV). This interface was loaded in a nano-indentation experiment on specimens with pre cracks that were fabricated using focused-ion-beam (FIB) milling. The elastic and plastic properties of the copper vias were characterized from micro-pillar compression experiments and associated finite element analyses. Analytical and numerical models were developed for extracting the parameters of traction-separation relation. The close agreement between the parameters extracted from these two approaches indicate that, with the proper choice of geometry, the interfacial parameters can be extracted directly in a relatively simple manner.
C. Wu et al., "Characterizing Traction-Separation Relations of TSV/SI Interfaces by Nanoindentation," Proceedings of the 2017 Annual Conference on Experimental and Applied Mechanics (2017, Indianapolis, IN), vol. 5, pp. 41 - 46, Springer Verlag, Jun 2017.
The definitive version is available at https://doi.org/10.1007/978-3-319-63405-0_7
2017 Annual Conference on Experimental and Applied Mechanics (2017: Jun. 12-15, Indianapolis, IN)
Civil, Architectural and Environmental Engineering
Center for High Performance Computing Research
Keywords and Phrases
Copper; Electronics packaging; Failure (mechanical); Finite element method; Integrated circuit interconnects; Integrated circuit manufacture; Ion beams; Microelectronics; Silicon; Stresses; 3-D integration; Analytical and numerical models; Micro-pillar compressions; Thermo-mechanical stress; Through-Silicon-Via; Through-Silicon-Via (TSV); Traction-separation relations; Three dimensional integrated circuits; 3D integration; Interfacial fracture; Through-silicon via
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Article - Conference proceedings
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01 Jun 2017