"With advancements in technology, transistor sizes are shrinking resulting in reduced power supply voltage and thereby reduced noise margin which makes the devices susceptible to electromagnetic noises. The trend of integrating more circuits on a single die at ever growing operating frequency increases interference among circuits and with the outside world. In order to make circuits electromagnetically compatible, it is essential to reduce emissions from the circuit and understand the causes of failure due to interference of noise from other sources coupling into the circuit so that a robust design can be created.
Two topics are explored in this thesis. The first topic deals with a case study of the immunity of low power Pierce crystal oscillators which includes the cause of failures and its mechanism. This knowledge can be used to design circuits which may have better immunity to those failure modes. The second chapter presents a preliminary study on using current mode logic (CML) for reducing emissions from the clock distribution network (CDN), which is one of the biggest contributors of emissions in a digital IC. A simple clock tree is designed with CML and is compared with a clock tree designed using standard single-ended CMOS logic, by analyzing its performance in terms of power consumption, noise, jitter, and rise and fall time"--Abstract, page iii.
Beetner, Daryl G.
Electrical and Computer Engineering
M.S. in Electrical Engineering
United States. Department of the Air Force
Missouri University of Science and Technology
Journal article titles appearing in thesis/dissertation
- IC immunity - impact of EFT on low power crystal oscillators and its failure mechanisms
- Impact of a CML-based clock distribution network on IC emissions
ix, 59 pages
© 2012 Vijay Kanagachalam, All rights reserved.
Thesis - Open Access
Library of Congress Subject Headings
Electromagnetic interference -- Control
Integrated circuits -- Design
Print OCLC #
Electronic OCLC #
Link to Catalog Record
Kanagachalam, Vijay, "Electromagnetic compatibility of integrated circuit clock design" (2012). Masters Theses. 6918.