Defect avoidance in nano crossbar architecture
Keywords and Phrases
Programmable gate macro block (PGMB)
"The thesis is organized into three papers...The first two papers evaluate three different logic mapping algorithms with defect avoidance to circumvent clustered defective cross points in nanowire reconfigurable crossbar architectures. The effectiveness of inherited redundancy and configurability utilization is demonstrated through extensive parametric simulations. The third paper discusses programming asynchronous nano crossbar architecture and demonstrates a method to find an optimal solution to the dimensions of proposed architecture through simulations"--Abstract, leaf iv.
McCracken, Theodore E.
Electrical and Computer Engineering
M.S. in Computer Engineering
University of Missouri--Rolla
Journal article titles appearing in thesis/dissertation
- Inherited redundancy and configurability utilization for repairing nanowire crossbars with clustered defects
- Cost-driven repairability optimization for nanowire crossbar architecture
- Programming asynchronous nano crossbar architecture
viii, 63 leaves
© 2007 Yadunandana Yellambalase, All rights reserved.
Thesis - Citation
Library of Congress Subject Headings
Print OCLC #
Link to Catalog Record
Full-text not available: Request this publication directly from Missouri S&T Library or contact your local library.http://laurel.lso.missouri.edu/record=b6000572~S5
Yellambalase, Yadunandana, "Defect avoidance in nano crossbar architecture" (2007). Masters Theses. 5976.