Masters Theses
Abstract
"A diagrammatic approach is presented for the synthesis of multilevel NAND networks realizing combinational logic expressions. The network synthesized is restricted to only uncomplemented inputs. The synthesis algorithm involves the determination of minimum sum of products and product of sums expressions for a Boolean function, construction of an α-ß diagram from these expressions followed by implementation with NAND gates directly from the diagram. The resulting network is a minimal or near minimal NAND gate realization of the given function. The algorithm is applicable to completely or incompletely specified Boolean functions and is extended to include NOR synthesis"--Abstract, page 2.
Advisor(s)
Tracey, James H.
Committee Member(s)
Betten, J. Robert
Carson, Ralph S.
Jones, R. E. Douglas
Department(s)
Electrical and Computer Engineering
Degree Name
M.S. in Electrical Engineering
Publisher
University of Missouri at Rolla
Publication Date
1966
Pagination
54 pages
Note about bibliography
Includes bibliographical references (page 53)
Rights
© 1966 Donald Robert Nelson, All rights reserved.
Document Type
Thesis - Open Access
File Type
text
Language
English
Subject Headings
Integrated circuits -- Design -- Mathematical models
Electronic circuit design
Digital electronics
Logic design -- Data processing
Thesis Number
T 1890
Print OCLC #
5975945
Electronic OCLC #
897205212
Link to Catalog Record
Recommended Citation
Nelson, Donald Robert, "An algorithm for the synthesis of NAND logic networks using a diagrammatic approach" (1966). Masters Theses. 5761.
https://scholarsmine.mst.edu/masters_theses/5761
