Masters Theses

Title

Model checking control communication of a FACTS device

Author

David Cape

Abstract

"This thesis concerns the design and verification of a real-time communication protocol for sensor data collection and processing between an embedded computer and a DSP. In such systems, a certain amount of data loss without recovery may be tolerated. The key issue is to design and verify the correctness in the presence of these lost data frames under real-time constraints. This thesis describes a temporal verification that if the end processes do not detect that too many frames are lost, defined by comparison of error counters against given threshold values, then there will be a bounded delay between transmission of data frames and reception of control frames. This verification and others presented herein were performed with the model checkers SPIN and RE-SPIN"--Abstract, leaf iii.

Advisor(s)

McMillin, Bruce M.

Committee Member(s)

Vojta, Thomas
Wilkerson, Ralph W.

Department(s)

Computer Science

Degree Name

M.S. in Computer Science

Publisher

University of Missouri--Rolla

Publication Date

Spring 2006

Pagination

vii, 80 leaves

Note about bibliography

Includes bibliographical references (page 39).

Rights

© 2006 David Andrew Cape, All rights reserved.

Document Type

Thesis - Citation

File Type

text

Language

English

Library of Congress Subject Headings

Computer software -- Verification
Fault-tolerant computing
Flexible AC transmission systems

Thesis Number

T 8952

Print OCLC #

82368341

Link to Catalog Record

Full-text not available: Request this publication directly from Missouri S&T Library or contact your local library.

http://laurel.lso.missouri.edu/record=b5771794~S5

This document is currently not available here.

Share

 
COinS