Memory DIMM DC Power Distribution Analysis and Design
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Abstract
DC power bus design is critical in meeting signal integrity (SI) and electromagnetic compatibility (EMC) requirements. A suitable modeling tool is beneficial to evaluate power bus design and develop design guidelines. This paper discusses difficulties met in evaluating the power distribution design on a dual inline memory module (DIMM) board, such as a power bus with arbitrary shape, parasitic inductance associated with vias, and so on. Moreover, some solutions are given in this paper. A simple cavity model with a segmentation method was employed to model a power bus with irregular shapes. The partial element equivalent circuit (PEEC) technique was applied to model the electrical properties of a high-speed via interconnect. For each proposed approach, the difference between the estimates and measurements demonstrates the application of these approaches in the DIMM DC power distribution analysis and design.
