Abstract
As Integrated Circuits are migrated to more advanced technologies, it has become clear that crosstalk noise is an important phenomenon that must be taken into account. Also, crosstalk noise has emerged as a serious problem in recent years, because more and more devices and wires have been packed on electronic chips. Despite being more immune to crosstalk noise than their ASIC (Application Specific Integrated Circuit) counterparts, the dense interconnected structures of FPGAs (Field Programmable Gate Arrays) invite more vulnerabilities to crosstalk noise. Due to the lack of electrical detail concerning FPGA devices it is quite difficult to test the faults caused by crosstalk noise. This paper proposes a new approach for detecting effects such as glitches and delays in transition due to crosstalk noise in FPGAs. This approach is similar to the BIST (Built-in Self-Test) technique in that it incorporates the test pattern generator to generate the test vectors and the analyzer to analyze the crosstalk faults without any extra overhead for testing. © 2008 IEEE.
Recommended Citation
W. K. Al-Assadi and S. Kakarla, "A BIST Technique for Crosstalk Noise Detection in FPGAs," Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 167 - 175, article no. 4641170, Institute of Electrical and Electronics Engineers, Dec 2008.
The definitive version is available at https://doi.org/10.1109/DFT.2008.14
Department(s)
Electrical and Computer Engineering
International Standard Serial Number (ISSN)
1550-5774
Document Type
Article - Conference proceedings
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2024 Institute of Electrical and Electronics Engineers, All rights reserved.
Publication Date
01 Dec 2008
