Analysis and Modeling of Crosstalk Noise in Domino CMOS Circuits
Domino CMOS logics offer designers with the advantage of most influential circuit design parameters viz., speed, higher integration density and lower power dissipation. This has made a common practice to use the domino CMOS in high performance integrated circuits. However, along with these positives comes inherently low crosstalk noise immunity. This reduced noise immunity of domino CMOS logics is continuously aggravating as recent trends in integrated circuit technology are constantly followed. Although several works investigate the problem of crosstalk noise at the inputs of domino circuits, crosstalk at the dynamic node of the domino circuits has been ignored. In this paper, we propose a model for crosstalk noise at the dynamic node of domino CMOS logic circuits. The model developed incorporates a newly derived switching threshold for the output static inverter in domino CMOS logics to more accurately predict the crosstalk noise immunity of the design. Application of this model can ensure immunity of domino circuits from crosstalk failures.
V. Sharma and W. K. Al-Assadi, "Analysis and Modeling of Crosstalk Noise in Domino CMOS Circuits," IEEE Region 5 Technical Conference, Institute of Electrical and Electronics Engineers (IEEE), Apr 2007.
The definitive version is available at http://dx.doi.org/10.1109/TPSD.2007.4380338
Electrical and Computer Engineering
University of Missouri Research Board
Keywords and Phrases
BiCMOS Logic Circuits; CMOS; Crosstalk
Library of Congress Subject Headings
Metal oxide semiconductors, Complementary
Article - Conference proceedings
© 2007 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.