Title

Continuous-Time Optimization of Gate Timing for Synchronous Rectification

Abstract

Synchronous rectifiers, which use a controlled MOSFET in place of a standard p-n or Schottky rectifier, are an important technology for low-voltage power converters. Conventional control techniques for synchronous rectification are often very conservative, however, leaving room for improvement. This paper presents a method for monitoring current flow to adaptively optimize the relative timing of two gate signals for a buck converter with synchronous rectification. Theoretical development is given, along with experimental results for two low-voltage converters.

Meeting Name

39th Midwest Symposium on Circuits and Systems (1996: Aug. 18-21, Ames, IA)

Department(s)

Electrical and Computer Engineering

Sponsor(s)

Sandia Laboratories
University of Illinois at Urbana-Champaign. Power Affiliates Program

Comments

This work was supported by Sandia National Laboratories as well as the Power Affiliates Program at the University of Illinois at Urbana-Champaign.

Keywords and Phrases

Electric Current Control; Gates (Transistor); MOSFET Devices; Optimization; Power Converters; Low Voltage Power Converters; Synchronous Rectifiers; Electric Rectifiers; Timing; Rectifiers; Pulse Width Modulation; MOSFET Circuits; Thyristors; Power MOSFET; Buck Converters; Adaptive Algorithm; Voltage; Switches; Power Convertors; Rectification; Optimisation; Continuous Time Systems; Timing

International Standard Book Number (ISBN)

780336364

Document Type

Article - Conference proceedings

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 1996 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

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