Progress in Representation and Validation of Physics-Based Via Models
Vias in printed circuit boards and chip packages are known to have significant detrimental impact on signal and power integrity in high-speed communication systems. Recently, concise equivalent circuit models for vias in multilayer configurations have been explored by the authors. The models accurately reflect the important physical properties of vias, since the topology utilized has a one-to-one correlation to the geometrical structure and the dimensions of the via. In this paper, the proposed physics-based via models are extended to include the interaction between two signal vias and a signal via plus a reference (ground) via. The models were then compared to experimental data obtained from several structures laid out on a 16-layer printed circuit board. The measurements performed using a 4-port vector network analyzer and the high performance recessed probe launching technique evidenced good correlation to 20 GHz and beyond.
C. Schuster et al., "Progress in Representation and Validation of Physics-Based Via Models," Proceedings of the 11th IEEE Workshop on Signal Propagation on Interconnects (2007, Genova, Italy), pp. 145-148, Institute of Electrical and Electronics Engineers (IEEE), May 2007.
The definitive version is available at https://doi.org/10.1109/SPI.2007.4512234
11th IEEE Workshop on Signal Propagation on Interconnects (2007: May 13-16, Genova, Italy)
Electrical and Computer Engineering
Keywords and Phrases
Chip Packages; Equivalent Circuit Model; Experimental Data; Geometrical Structure; Good Correlations; High-Speed Communication Systems; Multilayer Configuration; Physics-Based; Power Integrity; Vector Network Analyzers; Communication Systems; Data Flow Analysis; Electric Network Analysis; Electric Network Analyzers; Interchanges; Printed Circuit Boards; Printed Circuit Manufacture; Technical Presentations; Models
International Standard Book Number (ISBN)
0780370511; 9780780370517; 9781424412235
Article - Conference proceedings
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