Title

ESD Immunity Prediction of D Flip-Flop in the ISO 10605 Standard using a Behavioral Modeling Methodology

Abstract

As the ESD stress is becoming more and more important for integrated circuits (ICs), the ability to predict IC failures becomes critical. In this paper, an 18-MHz D flip-flop IC is characterized and its behavioral model is presented. The resulting IC model is validated in the setup according to the ISO 10605 standard. A complete model of the setup combining the IC behavioral model and the passive parts of the setup, including parallel and twisted pair harnesses, is built to estimate the failure prediction accuracy in a totally simulated environment. The results show that the model can predict the failure level with the error of less than 20% in parallel harness case and around 30% in the twisted pair case.

Department(s)

Electrical and Computer Engineering

Keywords and Phrases

Behavioral research; Electrostatic devices; Electrostatic discharge; Forecasting; Behavioral model; D flip flops; ESD stress; Failure levels; Failure prediction; Integrated circuits (ICs); Simulated environment; Twisted pair; Flip flop circuits

International Standard Serial Number (ISSN)

0018-9375

Document Type

Article - Journal

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 2015 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.


Share

 
COinS