ESD Immunity Prediction of D Flip-Flop in the ISO 10605 Standard using a Behavioral Modeling Methodology
As the ESD stress is becoming more and more important for integrated circuits (ICs), the ability to predict IC failures becomes critical. In this paper, an 18-MHz D flip-flop IC is characterized and its behavioral model is presented. The resulting IC model is validated in the setup according to the ISO 10605 standard. A complete model of the setup combining the IC behavioral model and the passive parts of the setup, including parallel and twisted pair harnesses, is built to estimate the failure prediction accuracy in a totally simulated environment. The results show that the model can predict the failure level with the error of less than 20% in parallel harness case and around 30% in the twisted pair case.
G. Shen et al., "ESD Immunity Prediction of D Flip-Flop in the ISO 10605 Standard using a Behavioral Modeling Methodology," IEEE Transactions on Electromagnetic Compatibility, vol. 57, no. 4, pp. 651-659, Institute of Electrical and Electronics Engineers (IEEE), Aug 2015.
The definitive version is available at http://dx.doi.org/10.1109/TEMC.2015.2418715
Electrical and Computer Engineering
Electromagnetic Compatibility (EMC) Laboratory
Keywords and Phrases
Behavioral research; Electrostatic devices; Electrostatic discharge; Forecasting; Behavioral model; D flip flops; ESD stress; Failure levels; Failure prediction; Integrated circuits (ICs); Simulated environment; Twisted pair; Flip flop circuits
International Standard Serial Number (ISSN)
Article - Journal
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