Title

Impact of Voltage Bias on Through Silicon Vias (TSV) Depletion and Crosstalk

Abstract

In this work the circuit segmentation approach for the modeling of Through Silicon Vias (TSV) is extended to the presence of time domain non linear phenomena such as depletion and capacitance hysteresis. Results are shown discussing the impact of the voltage bias on the above mentioned non-linear phenomena and their combined impact on crosstalk among TSV and between TSVs and active circuits.

Meeting Name

20th IEEE Workshop on Signal and Power Integrity (2016: May 8-11, Turin, Italy)

Department(s)

Electrical and Computer Engineering

Research Center/Lab(s)

Center for High Performance Computing Research

Keywords and Phrases

Bias voltage; Capacitance; Crosstalk; Electronics packaging; Hysteresis; Image segmentation; Integrated circuit interconnects; Reconfigurable hardware; Silicon; Active circuits; Circuit segmentation; Modelin; Non-linear phenomena; Nonlinear effect; Through silicon vias; Time domain; Voltage bias; Three dimensional integrated circuits; circuit modelin

International Standard Book Number (ISBN)

978-150900349-5

Document Type

Article - Conference proceedings

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 2016 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

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