This paper presents a model for analyzing the reliability of a clockless wave pipeline as an intellectual property (IP) core for embedded design. This design requires different clocking requirements by each embedded IP core during integration. Therefore, either partial or global lack of synchronization of the embedded clocking is considered for the data flow. The clockless wave pipeline represents an alternative to a traditional pipeline scheme; it requires an innovative computing model that is readily suitable for high-throughput computing by heterogeneous IP logic cores embedded in system-on-chip (SoC). A clockless wave pipeline technique relies on local asynchronous operation for seamless integration of a combinational core into an SoC. The basic computational components of a clockless wave pipeline are the datawaves, together with the request signals and switches. The coordination of the processing of the datawaves throughout the pipeline by the request signals is accomplished with no intermediate access in the clock control. Furthermore, the reliability of clockless-wave-pipeline-based cores is of importance when designing a reliable SOC. In this paper, the reliability in the clockless operations of the wave pipeline is analyzed by considering the datawaves and the request signals. The effect of the so-called out-of-orchestration between the datawaves and the request signals (which is referred to as a datawave fault) is proposed in the reliability analysis. A clockless-induced datawave fault model is proposed for clockless fault-tolerant design.
T. Feng et al., "Reliability Modeling and Analysis of Clockless Wave Pipeline Core for Embedded Combinational Logic Design," IEEE Transactions of Instrumentation and Measurement, Institute of Electrical and Electronics Engineers (IEEE), Jul 2010.
The definitive version is available at http://dx.doi.org/10.1109/TIM.2009.2030917
Electrical and Computer Engineering
National Science Foundation (U.S.)
Keywords and Phrases
Embedded Intellectual Property (IP) Core; Fault Tolerance; System-On-Chip (SoC); Wave Pipeline; Asynchronous circuits; Reliability
Article - Journal
© 2010 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.