This paper focuses on implementing a 2s complement 8x8 dual-rail bit-wise pipelined multiplier using the asynchronous null convention logic (NCL) paradigm. The design utilizes a Wallace tree for partial product summation, and is implemented and simulated in VHDL, the transistor level, and the physical level, using a 1.8V 0.18mum TSMC CMOS process. The multiplier is realized using both static and semi-static versions of the NCL gates; and these two implementations are compared in terms of area, power, and speed.
R. Sankar et al., "Implementation of Static and Semi-Static Versions of a 24+8x8 Quad-rail NULL Convention Multiply and Accumulate Unit," Proceedings of the IEEE Region 5 Technical Conference, 2007, Institute of Electrical and Electronics Engineers (IEEE), Apr 2007.
The definitive version is available at http://dx.doi.org/10.1109/TPSD.2007.4380351
IEEE Region 5 Technical Conference, 2007
Electrical and Computer Engineering
National Science Foundation (U.S.)
Keywords and Phrases
CMOS Digital Integrated Circuits; Digital Simulation; Hardware Description Languages; Logic Design; Logic Gates; Multiplying Circuits; Trees (Mathematics)
Library of Congress Subject Headings
Metal oxide semiconductors, Complementary
VHDL (Computer hardware description language)
Article - Conference proceedings
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