Abstract

This paper focuses on implementing a 2s complement 8x8 dual-rail bit-wise pipelined multiplier using the asynchronous null convention logic (NCL) paradigm. The design utilizes a Wallace tree for partial product summation, and is implemented and simulated in VHDL, the transistor level, and the physical level, using a 1.8V 0.18mum TSMC CMOS process. The multiplier is realized using both static and semi-static versions of the NCL gates; and these two implementations are compared in terms of area, power, and speed.

Meeting Name

IEEE Region 5 Technical Conference, 2007

Department(s)

Electrical and Computer Engineering

Sponsor(s)

National Science Foundation (U.S.)

Keywords and Phrases

CMOS Digital Integrated Circuits; Digital Simulation; Hardware Description Languages; Logic Design; Logic Gates; Multiplying Circuits; Trees (Mathematics)

Library of Congress Subject Headings

Asynchronous circuits
Metal oxide semiconductors, Complementary
VHDL (Computer hardware description language)

Document Type

Article - Conference proceedings

Document Version

Final Version

File Type

text

Language(s)

English

Rights

© 2007 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

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