Abstract
Self-timed multipliers, designed using the delay-insensitive null convention logic (NCL) paradigm, were analyzed. NCL require less power, generate less noise, produce less electromagnetic interference, and allow easier reuse of components. Simulation results show a large variance in circuit performance in terms of power, area, and speed. NCL paradigm also represent bit-serial, iterative, and fully parallel multiplication architectures. They reduce the effort required to ensure correct operation under all timing scenarios, compared to equivalent synchronous designs.
Recommended Citation
S. K. Bandapati et al., "Design and Characterization of Null Convention Self-Timed Multipliers," IEEE Design and Test of Computers, vol. 20, no. 6, pp. 26 - 36, Institute of Electrical and Electronics Engineers (IEEE), Nov 2003.
The definitive version is available at https://doi.org/10.1109/MDT.2003.1246161
Department(s)
Electrical and Computer Engineering
Sponsor(s)
University of Missouri Research Board
Keywords and Phrases
VLSI; Asynchronous Circuits; Bit-Serial Architecture; Circuit Performance; Circuit Simulation; Clockless Digital VLSI Circuit; Convention Logic; Delay-Insensitive Method; Delay-Insensitive Signaling Scheme; Digital Arithmetic; Iterative Architecture; Logic Design; Multiplying Circuits; Parallel Architectures; Parallel Multiplication Architecture; Self-Timed Multiplier Design
International Standard Serial Number (ISSN)
0740-7475
Document Type
Article - Journal
Document Version
Final Version
File Type
text
Language(s)
English
Rights
© 2003 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
Publication Date
01 Nov 2003
Comments
We thank the University of Missouri Research Board for the funding that made this work possible.