An asynchronous nanowire crossbar architecture has been recently proposed to eliminate the clock distribution network from conventional clocked counterpart. The proposed clock-free architecture is envisioned to enhance the manufacturability with simpler periodic structure and to improve the robustness by removing various timing-related failure modes. Even though the proposed clock-free architecture has numerous merits over its clocked counterpart, it is still not free from high defect rates induced by nondeterministic nanoscale assembly. In order to address this issue, our research team has been working on developing test schemes for effective mapping of threshold gates onto programmable gate macro blocks (PGMB). We have come up with a novel functional test approach which uses prioritized input tuples to effectively stimulate coinciding defects in configured PGMB. Numerous preliminary plots and results obtained till date prove that this scheme can be used to achieve high test efficiency for any threshold gate. The main motivation behind this research is to propose a comprehensive test scheme which can achieve high enough test coverage with acceptable test overhead. Parametric simulation results using MATLAB have been used to show potential performance of this testing scheme.
S. Venkateswaran and M. Choi, "Post-Configuration Testing of Asynchronous Nanowire Crossbar Architecture," Proceedings of the 8th IEEE Conference on Nanotechnology, 2008, Institute of Electrical and Electronics Engineers (IEEE), Aug 2008.
The definitive version is available at http://dx.doi.org/10.1109/NANO.2008.269
8th IEEE Conference on Nanotechnology, 2008
Electrical and Computer Engineering
Keywords and Phrases
Logic Testing; Nanoelectronics; Nanowires; Progammable Logic Arrays; Timing; Asynchronous circuits
Article - Conference proceedings
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