Abstract

It is often assumed that the faults in storage elements (SEs) can be modeled as output/input stuck-at faults of the element. They are implicitly considered equivalent to the stuck-at faults in the combinational logic surrounding the SE cells. Transistor-level faults in common SEs are examined here. A more accurate higher level fault model for elementary SEs that better represents the physical failures is presented. It is shown that a minimal (stuck-at) model may be adequate if only modest fault coverage is desired. The enhanced model includes some common fault behaviors of SEs that are not covered by the minimal fault model. These include data-feedthrough and clock-feedthrough behaviors, as well as problems with logic level retention. Fault models for complex SE cells can be obtained without a significant loss of information about the structure of the circuit. The detectability of feedthrough faults is considered.

Department(s)

Electrical and Computer Engineering

Keywords and Phrases

Clock-Feedthrough Behavior; Data-Feedthrough Behavior; Fault Behaviors; Fault Coverage; Fault Detectability; Fault Location; Fault Model; Logic Level Retention; Logic Testing; Physical Failures; Sequential Circuits; Storage Elements; Transistor-Level Faults

International Standard Serial Number (ISSN)

1063-8210

Document Type

Article - Journal

Document Version

Final Version

File Type

text

Language(s)

English

Rights

© 1993 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

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